NI LabVIEW DSP Design Module software is now available for early adopters. To learn more about the LabVIEW DSP Design Module Early Access Program, email dspdesign@ni.com.
LabVIEW DSP Design for the LabVIEW FPGA Module reduces the complexity of designing real-time DSP subsystems for high-speed field-programmable gate array (FPGA) applications such as RF and communications. Using a stream-based graphical abstraction, you can rapidly implement an algorithm, explore design trade-offs, and generate an optimized FPGA implementation. You can then integrate the resulting implementation as a modular part of a larger LabVIEW FPGA-based application.
Rapidly Prototype Real-Time FPGA-Based DSP Subsystems
The intuitive language of LabVIEW DSP Design extends LabVIEW FPGA by providing a target-independent description of the DSP algorithm. Multirate DSP algorithms are described by combining high-level functional blocks that explicitly describe sample counts at the inputs and outputs of each block. LabVIEW DSP Design combines the sample counts of the inputs and outputs of each block with known cycle-level timing to determine optimal scheduling, memory, and FPGA resource utilization. You can compile the resulting algorithms into reusable blocks and integrate them into larger LabVIEW FPGA-based applications for execution on compatible NI reconfigurable I/O (RIO) FPGA devices.
Explore Design Trade-Offs Early in the Design Process
In addition to cycle-accurate simulation for algorithmic verification, LabVIEW DSP Design helps you achieve a detailed look at execution scheduling. Using the Scheduling View, you can analyze trade-offs between latency and resource utilization. By enabling pipelining and changing memory buffer sizes, you can profoundly impact how high-speed, multirate applications execute. With LabVIEW DSP Design, you can effectively understand and optimize these design aspects early in the design process.
