LabVIEW FPGA Floating-Point Library by NI Optimized Floating-Point Library for LabVIEW FPGA

  • Eliminate time-consuming and error-prone floating- to fixed-point conversions
  • Avoid numerical stability issues from fixed-point control design and simulation algorithms
  • Minimize effort to move complex algorithms from desktop or real-time environments to the FPGA
  • Develop reusable, universal IP cores for LabVIEW FPGA likely to work in many applications
  • Eliminate the need for extensive error handling for fixed-point algorithms
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Floating-point math operations on FPGAs are important for many control and simulation applications. In LabVIEW FPGA, most math operation nodes in the Numeric and Comparison palette support the single-precision floating-point data type. However, these primitive nodes cannot run inside a single-cycle Timed Loop (SCTL) to achieve higher performance. Additionally, these nodes cannot be configured for resource optimization at the cost of performance.

The LabVIEW FPGA Floating-Point Library solves this problem by providing IP that can be optimized in the following ways:

1. Resource Optimization - IP designed to minimize resource usage by running outside the SCTL. Resources can be shared if the same instance of an IP is dropped multiple times in a user’s application.

2. Performance Optimization - IP that offers better timing performance by running in an SCTL. The target clock rate for all inside the SCTL IP is 40 MHz. The IP is designed to have low latency based on the clock rate requirement.

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