The NI LabVIEW FPGA IP Builder add-on to the LabVIEW FPGA Module helps you easily generate high-performance FPGA IP by combining high-level synthesis (HLS) technology with the power of LabVIEW graphical development and NI FPGA-based hardware.

With LabVIEW FPGA IP Builder, you can generate custom algorithms like filters, encoders/decoders, and other analysis functions for use in NI FPGA-based applications such as machine vision, control and simulation, sound and vibration, digital signal processing, and communication systems without requiring knowledge of hardware description languages (HDLs). The tool also provides high-quality resource-use and performance results.

This add-on helps you use the LabVIEW graphical dataflow language to describe your algorithms. Because of user-provided directives that capture design constraints and help guide the LabVIEW FPGA IP Builder code generator, you do not have to learn more advanced LabVIEW FPGA optimization concepts. The tool uses state-of-the-art HLS technology to help you apply these advanced concepts, such as pipelining, resource multiplexing, and loop unrolling, to generate resource- and timing-optimized FPGA IP. With LabVIEW FPGA IP Builder, you can match or exceed the results obtained through manual LabVIEW FPGA design optimization and focus on the high-level design of your algorithms. Because design directives are stored separately from algorithm code, you can quickly explore design trade-offs and easily enable IP reuse to meet new design requirements. This tool can infer and optimize the use of resources such as multipliers and block RAM to provide early estimates for resource use and timing.

LabVIEW FPGA IP Builder supplements the capabilities of the LabVIEW FPGA design platform by helping you build highly optimized IP when LabVIEW FPGA does not provide the desired function or when a function does not meet your performance or resource-use needs. IP generated by LabVIEW FPGA IP Builder is automatically packaged in an IP Integration Node for use within a single-cycle Timed Loop in your LabVIEW FPGA design.

For information on system requirements, view the Resources tab.

Additional Product Information

• Manuals  
• Evaluation Software  

Related Information

• System Requirements for NI LabVIEW FPGA IP Builder
• General System Requirements for NI LabVIEW Development Systems and LabVIEW Modules
• LabVIEW 2012 FPGA IP Builder Release Notes
• Learn More About LabVIEW FPGA IP Builder
• LabVIEW 2012 FPGA IP Builder Help