Note: IP Builder is now part of the LabVIEW FPGA module. See the Resources tab for details.
With the NI LabVIEW FPGA IP Builder add-on to the LabVIEW FPGA Module you can easily optimize the performance and resource utilization of your LabVIEW FPGA VIs by combining high-level synthesis (HLS) technology with the power of LabVIEW.
Filters, encoders/decoders, and other analysis functions for use in NI FPGA-based applications such as machine vision, control and simulation, sound and vibration, digital signal processing, and communication systems can be automatically optimized with LabVIEW FPGA IP Builder without requiring knowledge of hardware description languages (HDLs) or advanced optimization tricks that reduce the portability and readability of your code.
This add-on helps you use the LabVIEW graphical dataflow language to describe your algorithms. You can make use of arrays and nested loops within your code and still obtain a highly-optimized version of the algorithm for use on NI FPGA based hardware. The tool works by taking user-provided directives that capture design constraints and help guide the LabVIEW FPGA IP Builder code generator. The tool uses state-of-the-art HLS technology to help you apply advanced optimization techniques, such as pipelining, resource multiplexing, and loop unrolling, to generate resource- and timing-optimized FPGA IP.
By using LabVIEW FPGA IP Builder, you can typically match or exceed the results obtained through manual LabVIEW FPGA design optimization and focus on the high-level design of your algorithms. Because design directives are stored separately from algorithm code, you can quickly create multiple sets of directive for the same IP to explore design trade-offs and easily reuse IP reuse to meet new design requirements. This tool can infer and optimize the use of resources such as multipliers and block RAM to provide early estimates for resource use and timing. IP generated by LabVIEW FPGA IP Builder is automatically packaged in an IP Integration Node for use within a single-cycle Timed Loop in your LabVIEW FPGA design.
For information on system requirements, view the Resources tab.