- Multiple synchronized inputs and outputs
- Up to 20 MHz real-time bandwidth
- Up to 200 MS/s and 14-bit resolution
- User-defined Xilinx FPGAs
- Programmed with the NI LabVIEW FPGA Module
- Built-in digital upconverters and downconverters
NI reconfigurable I/O (RIO) intermediate frequency (IF) transceivers are user-programmable instruments that incorporate multiple inputs and outputs and target software-defined radio, automated spectral monitoring, real-time spectral analysis, and real-time test applications such as RFID test or cellular base station emulation. They feature high-speed, high-resolution digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) with built-in 20 MHz bandwidth digital upconverters and downconverters. The modules also include high-performance Xilinx field-programmable gate arrays (FPGAs) that you can program using the NI LabVIEW FPGA Module to easily handle complex and high-speed signal processing, analysis, and modulation tasks.
Connectivity to NI RF Hardware
When paired with the NI PXI-5600 downconverter and NI PXI-5610 upconverter, the NI IF transceivers enable user-programmable FPGA-based radio frequency (RF) applications at frequencies up to 2.7 GHz and instantaneous bandwidths up to 20 MHz. With an NI PXIe-1065 chassis, you can connect two upconverters and two downconverters to a single NI PXIe-5641R for synchronized acquisition and generation.
High-Speed Data Streaming
With high-performance storage solutions such as the NI 8260 1 TB in-chassis data storage module, you can continually record time-domain IF data at more than 100 MB/s while performing measurements and analysis in real time on the FPGA of the transceiver module.
Programming Considerations
You can program the NI IF transceivers in three ways. First, to minimize the time to first measurement, use a precompiled FPGA personality from NI along with an easy-to-use API on the host. For more advanced FPGA-defined applications, use LabVIEW FPGA and the NI-RIO driver for high-speed communication between and graphical programming of both the host and FPGA. Finally, the asynchronous timing wire, the latest addition to the LabVIEW FPGA Module, provides asynchronous communication between signal acquisition, processing, and generation blocks on the LabVIEW FPGA block diagram.
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