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Why am I Getting a Broken Arrow When I Know my Array is Fixed Size? In LabVIEW FPGA I have code that creates an array which will always have the same size. However, I get a broken run arrow with an error stating: Arrays must be fixed size in current target.An example of this would be a For Loop which runs a fixed URL: http://digital.ni.com/public.nsf/allkb/83FF1EB9DA561820862574BF007C654F

Error -63004 During Code Generation Stage for an FPGA VI On trying to compile my FPGA program, I get error 63004 with the error message:An internal software error has occurred. Please contact National Instruments technical support at ni.com/support with the following URL: http://digital.ni.com/public.nsf/allkb/02ABE4E8C09112FF862574B4007B9EB2

Compiling an FPGA VI Programmatically I can compile an FPGA VI by either clicking the run button or right-clicking on the FPGA VI in the project explorer and selecting Compile... However, I would like to create a VI to programmatically compile a series of FPGA VIs that I have in my project explorer. Is there a URL: http://digital.ni.com/public.nsf/allkb/3A3E0C1B1013BFA3862574B3007A313C

Why Does My Host FPGA FXP Read Write Control Node Cause an Error 'Xnode Is Not Executable'? My Host FPGA Interface Read/Write Control Node is reading or writing to a fixed point control or indicator on my FPGA VI. However, my host VI has a broken run arrow. When I list the errors, the error says the Xnode is not URL: http://digital.ni.com/public.nsf/allkb/6CD1E3201007D1B2862574A40075D384

Why Does It Take So Long to Compile an FPGA VI for a cRIO in Hybrid Mode I have a cRIO set up such that some of my modules are utilizing the Scan Mode and some of my modules have custom code written in an FPGA VI. The custom code for my FPGA VI is very simple but the compile time is much longer than I would have expected. Why does it take so long to compile? URL: http://digital.ni.com/public.nsf/allkb/61276465E3043C0C8625749E005CC8A1

为什么在混合模式下的cRIO中编译一个FPGA VI需要很长时间？ 我有这样一个cRIO的配置，某些模块使用了Scan Mode，有些模块使用自定义的FPGA VI。自定义的FPGA VI是很简单的，但是编译时间比我预想的长很多。为什么需要这么长的时间？ URL: http://digital.ni.com/public.nsf/allkb/6AEA30128C7DCA8D862574D1004EE9C4

How Can I Add My Reusable VIs to FPGA Functions Palette? I am not able to add user libraries to my FPGA module as the functions palette does not have any option to add user libraries like the LabVIEW Development Environment. URL: http://digital.ni.com/public.nsf/allkb/28DF1C06CA6E048686257498001239F4

Why Do I Receive Error -63193 When Attempting to Detect an Existing FPGA Target? I have created a LabVIEW project and want to add an FPGA target. When I select Existing target or device, I get a message saying Error -63193 occurred at an unidentified location. Why does this error occur? URL: http://digital.ni.com/public.nsf/allkb/ECD4F3D186F9C60B862574890050C8D4

cRIOのFPGA上のVIをcRIOの電源投入と同時に実行させる方法に関して cRIOのシャーシ内のFPGAにあるVIが、cRIOに電源を入れる時に自動的に実行されるような設定はできますか。できる場合、その方法を教えてください。 URL: http://digital.ni.com/public.nsf/allkb/E39F42A27E79A27086257478003B5B6B

Why Do I Get 'error generating preview' When Trying to Build an Installer Using the Open FPGA VI Reference? I am able to build an executable of an application using Open FPGA VI Reference. But I receive error generating preview when building an installer with this executable. URL: http://digital.ni.com/public.nsf/allkb/0760ECF685DBC13B8625747300655BDB