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Extra Pulse Generated By NI PCIe-8255R When Using Close FPGA VI Reference I am generating a pulse train from my NI PCIe-8255R. When I close the FPGA reference to my device it generates an unexpected extra pulse. Why is this happening, and how do I prevent it? URL: http://digital.ni.com/public.nsf/allkb/180C2A1C1112BA2C862575E1006D6B6E

NI 9870 Does not show up in FPGA IO Constant I have placed an I/O constant or I/O control as the input to my FPGA I/O Method Node or FPGA I/O Property Node and want to select my 9870/9871 module or one of it's ports. Why does it not show up as one of the selections? URL: http://digital.ni.com/public.nsf/allkb/9BF90AF3B60A5458862575DE00541F3F

FPGA Compile Error: Cannot find input file 'toplevel_gen_map.ncd' Why do I get the following error when I try to compile my FPGA code: FPGA Compile Error: Cannot find input file "toplevel_gen_map.ncd"? The compile time also takes an unusually long time. URL: http://digital.ni.com/public.nsf/allkb/3C711A7642AD9F0D862575D10050FA61

Recuperando un Valor Numérico para la Frecuencia de Muestreo de un Módulo DSA en LVFPGA Utilizando un Nodo de Porpiedad de E/S (I/O), puedo obtener el control enumerado (enum) de los datos de la frecuencia de muestreo de un módulo de Adquisición Dinámica de Señal (DSA). Sin embargo, este enum no provee un valor numérico para la frecuencia de muestreo (50k), entrega un valor para el URL: http://digital.ni.com/public.nsf/allkb/7ED1F0511BC5079A862575DA005AEA47

Retreiving a Numeric Value for a DSA Module's Sampling Rate in LVFPGA Using a IO Property Node, I can retrieve the data rate enum from a Dynamic Signal Acquisition module. However, this enum does not provide a numeric value for the sampling rate (50k), but rather a value for the enum (2).I want to get the numeric value for the sampling rate programatically so I can URL: http://digital.ni.com/public.nsf/allkb/E9C03C26A0BB314F862575C80066EB92

Compile Error When Running FPGA VI With An Array I have an FPGA VI which uses an array. When I compile the VI, the compiler returns the error ERROR:Xflow – Program xst returned error code 6. Aborting flow execution. Why does this occur? How can I prevent it? URL: http://digital.ni.com/public.nsf/allkb/57F6F33E799C7BF6862575C500651551

Can I Create Socketed CLIP For My R-Series Board? I would like to connect my VHDL core directly to my R-Series input and output. Can I use Socketed CLIP to do this? URL: http://digital.ni.com/public.nsf/allkb/E7A1B777BCBAFA32862575C4007D5972

Using Both Scan Mode and FPGA Mode On My cRIO Simultaneously. I want to use some of my cRIO modules in Scan Mode and some in FPGA Mode. There is no explicit option to do this in the chassis properties. How can I do this? URL: http://digital.ni.com/public.nsf/allkb/0DB7FEF37C26AF85862575C400531690

How Do I Convert A Raw Value To Fixed Point In FPGA? I am using a function in FPGA that only outputs raw data. But my IO Node is configured for fixed point data. How can I convert my raw values to fixed point? URL: http://digital.ni.com/public.nsf/allkb/BBBD1A290BDDBF50862575AE0006124C

Why Is PID.vi Not Supported on the 9505? I opened the Velocity Control (closed loop) – NI 9505.lvproj example and opened the Velocity Control (closed loop) – NI 9505(FPGA).vi. The Context Help (shown below) for the PID VI says this VI is no longer supported and to use the PID (FPGA) Express VI instead. However, when I replace the older URL: http://digital.ni.com/public.nsf/allkb/597AAAAEDD6716AE862575AD007B889F