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我如何在程式中重置〈Reset〉我的 CompactRIO 控制器 我想要在程式中重置我的 CompactRIO 控制器。這是可行的嗎？ URL: http://digital.ni.com/public.nsf/allkb/87DF722004EB493B8625738E002AF49D

어떻게 하면 CompactRIO 컨트롤러를 프로그램적으로 리셋할수 있습니까? CompactRIO 컨트롤러를 프로그램적으로 리셋하고 싶습니다. 가능합니까? URL: http://digital.ni.com/public.nsf/allkb/8800E69A66D5F316862570B300023AFD

Error -61024 from Open FPGA VI Reference VI My host VI returns error -61024 from the Open FPGA VI Reference node. Why is this happening? URL: http://digital.ni.com/public.nsf/allkb/D38422861E5BBD3B8625704300577849

Open FPGA VI Reference VI 에서의 에러 -61024 저의 host VI가 Open FPGA VI Reference 노드로부터 에러 -61024가 발생합니다. 왜 발생하는 것입니까? URL: http://digital.ni.com/public.nsf/allkb/F2E6C419EF5541B98625704B0003D441

How Do I Configure the CompactRIO Expansion Chassis for Use with an R-Series Device? How do I connect and configure my R Series Expansion Chassis, cRIO-9151, to my R Series Intelligent DAQ Device? URL: http://digital.ni.com/public.nsf/allkb/A8F957BF50B3DA4486256FCF0064FCD7

R 시리즈 장비와 사용할 수 있는 CompactRIO 확장 샤시는 어떻게 구성합니까? CompatRIO 제품군 중 R 시리즈 확장 샤시(cRIO-9151)는 PXI-7831R, PXI-7811R, PCI-7811R에 포함되어 있는 산업용 I/O, 절연 그리고 시그널 컨디셔닝을 제공한다. 어떻게 cRIO-9151과 연결하고 구성하는지, 그리고 각 R 시리즈 장비에 얼마나 많은 확장 샤시를 사용할 수 있습니까? URL: http://digital.ni.com/public.nsf/allkb/8BA29CCD625AB1BE8625701E0081F4B5

How is the Timeout Specified for the 'Wait on...' I/O Method Node Under FPGA Specifying Timeout When specifying the timeout on the wait on rising edge, falling edge, any edge, high level, low level, there's no information in LabVIEW 8.2 or earlier on what units you use. What units do I use? URL: http://digital.ni.com/public.nsf/allkb/0D8325309894115286256F3B00341159

Can I use LabVIEW 7.0 with FPGA 1.0 on the PCI-7831R or the PXI-7811R? I am using LabVIEW 7.0 with FPGA Module 1.0 and NI-RIO 1.1. I found in the readme for NI-RIO that it supports LabVIEW 7.x and that it supports the PCI/PXI-7831R and the PXI-7811R. Does this mean I can use LabVIEW 7.0 and FPGA Module 1.0 with the PCI-7831R or the PXI-7811R if I have NI-RIO 1.1? URL: http://digital.ni.com/public.nsf/allkb/52C3EE437A633B9986256F0C006DA4DD

Why Are the Digital Output Lines of My R Series Device Going High When I Run My Host Interface VI? When I run my host interface VI to control the VI running on the FPGA on my R Series device, I notice that the digital output lines of the R Series device go high when my host interface calls the Close FPGA VI Reference.vi. How can I fix this? URL: http://digital.ni.com/public.nsf/allkb/48A789BB01BF755686256EEA0007F62C

Error when Building FPGA VI with 16 32-bit Multiplication Functions I have an FPGA VI that has 16 32-bit multiplication functions. When I try to build it, at the end of the compilation, I get an error from the LabVIEW FPGA Compile Server. Why am I getting this error, and how can I prevent it? URL: http://digital.ni.com/public.nsf/allkb/E92FB7824198EF6086256E92007179C0