'Not Responding to Base Address' Error in MAX when Running Traditional DAQ Test Panel with PCI-DIO-32Hs Board Connected to SSR Backplane.
I have a PCI-DIO-32HS connected to a SSR backplane. When I open a Traditional NI-DAQ driver test panel in MAX, it gives me a 'Not Responding to Base Address' error.
URL: http://digital.ni.com/public.nsf/allkb/DD63499842CCE47486257243000F8C46
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What is the Value of +5V I/O Connector Pin on PCI-6515 when Input to VCC is Less Than 10VDC?
In the specifications for the PCI-6515 it is mentioned that the +5V I/O connector pin will output 5V if VCC is greater than 10VDC, but what happens when the input to VCC is between 5V and 10V?
URL: http://digital.ni.com/public.nsf/allkb/ECF78765C6EE6A72862572410075C974
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Exporting the NI-HSDIO Generation Session Sample Clock
If I configure my NI-HSDIO generation application to export the sample clock, why do I see this sample clock before I initiate the session?
URL: http://digital.ni.com/public.nsf/allkb/AB13E3DBC0D959A38625723C00757C8D
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NI-HSDIO Dynamic Generation and Acquisition Shipping Example Triggering
I am developing an application based upon the NI-HSDIO shipping example Dynamic Generation and Acquisition-Source Synchronous (TClk).vi. In this example, the generation session is configured to export the Data Active Event to PFI 1 to serve as a start trigger for the acquisition
URL: http://digital.ni.com/public.nsf/allkb/F6BE8B5B5588B60C8625723C006A240F
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Toggling Rates for Digital Devices
The specifications for my digital device state that the maximum clock rate of my device is 50 MHz. However, when I output a toggled signal (0, 1, 0, 1, …), the frequency that I’m seeing on my oscilloscope is only half of that maximum clock rate. Why is this so?
URL: http://digital.ni.com/public.nsf/allkb/5640FADF5392F1308625723800036AAA
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Why Do My Digital Output Lines Not Output a Digital High?
I have a device with digital output lines. When I test the card with a digital multimeter, the outputs will not output a logic high when set to high. What is wrong with my card?
URL: http://digital.ni.com/public.nsf/allkb/B8D3301AEE5DECF58625723500028138
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Handling HSDIO Data Delays Greater Than 100%
NI-HSDIO devices (654x, 655x, 656x) provide a property called Data Position.Delay to account for delays caused by driving data over a transmission line. However, the programmable delay has a maximum range of 100% of a sample clock cycle. How can a delay of greater than 100%
URL: http://digital.ni.com/public.nsf/allkb/53BFD784329FF5BD86257210005D2004
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Input Capacitance for NI 654x High Speed Digitial I/O Devices
For the NI 654x devices that use the 1 m SHC68-C68-D2 cable, the cable is rated for a typical 28 pF / ft, resulting in a capacitance of roughly 92 pF. Combined with the capacitance of the connector leads, the total capacitance of the cable can be estimated at 100pF.
URL: http://digital.ni.com/public.nsf/allkb/EAA7AD955745C0678625720D0050BE03
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Per Cycle Tristate Programming with NI-HSDIO
How do I program my NI-HSDIO device to tristate on a per-channel, per-cycle basis? When I try to implement this in LabVIEW, I get an "Error -1074118585 occurred at niHSDIO Write Named Waveform (WDT).vi"
URL: http://digital.ni.com/public.nsf/allkb/9F9C39A8548A01FE8625720D007330EF
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External Clocking for HSDIO Devices
I would like to use an external clock to acquire and generate data on my HSDIO devices, at frequencies that may not be integer divisors of the onboard clock. What options do I have?
URL: http://digital.ni.com/public.nsf/allkb/B36B9D1B2FC55CBF862571F9000072BA
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