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How Do I Synchronize the FPGA Clock in my R-Series Intelligent I/O Board to my PXI clock? I would like to synchronize the FPGA clock of my R-series PXI board to the 10 MHz clock in the PXI backplane. Where can I select this setting? URL: http://digital.ni.com/public.nsf/allkb/53306F0FDA486B298625738A007B130F

How Do I Synchronize the FPGA Clock in my R-Series Intelligent I/O Board to my PXI clock? I would like to synchronize the FPGA clock of my R-series PXI board to the 10 MHz clock in the PXI backplane. Where can I make this setting? URL: http://digital.ni.com/public.nsf/allkb/D108D4AF937524CA862570FF004C2A48

Analog Input Mode Configuration For 783xR Series Boards Problem: How do I configure the analog input mode of my 783xR FPGA board? Solution: In LabVIEW 8.0 and higher, the analog input mode of the FPGA board is software selectable from within the Project Explorer. URL: http://digital.ni.com/public.nsf/allkb/08EF26D2E9041BC6862570E0001E442E

How to Reconnect to the LabVIEW FPGA Compile Server I disconnected my compiler client from the compile server and when I tried to reconnect to the FPGA VI by hitting Build in FPGA Project Manager it will recompile again. How can I reconnect to the server without compiling the VI again? URL: http://digital.ni.com/public.nsf/allkb/417E4AE5B5C74BEE862570BB00087933

How Do I Programmatically Reset My CompactRIO Controller? I would like to be able to programmatically reset my CompactRIO controller. Is this possible? URL: http://digital.ni.com/public.nsf/allkb/25825D24D1DF688D8625709D0053FF68

Error -61024 from Open FPGA VI Reference VI My host VI returns error -61024 from the Open FPGA VI Reference node. Why is this happening? URL: http://digital.ni.com/public.nsf/allkb/D38422861E5BBD3B8625704300577849

Accessing Unused Lines on Connector when Using CompactRIO Expansion Chassis I am using a cRIO-9151 expansion chassis with my PXI-7831R device. The cRIO chassis is connected to Connector 1, which is one of the DIO connectors of the PXI-7831R device. I am looking for documentation on which lines of that DIO connector are mapped and used by the expansion chassis. URL: http://digital.ni.com/public.nsf/allkb/2C12013BB5F090B086256FDD004565A2

How Do I Configure the CompactRIO Expansion Chassis for Use with an R-Series Device? How do I connect and configure my R Series Expansion Chassis, cRIO-9151, to my R Series Intelligent DAQ Device? URL: http://digital.ni.com/public.nsf/allkb/A8F957BF50B3DA4486256FCF0064FCD7

How Do I Set the LabVIEW Execution Target to be a Remote FPGA Card on an RT System? I have a remote PXI system running Real-Time and I am writing an application on my desktop PC that will run on the FPGA card in the RT system. How do I setup my system to run the code on the remote FPGA card and not just in Real-Time? URL: http://digital.ni.com/public.nsf/allkb/8980356DA789165E86256F8E00462FE4

Choosing Pull-Up Resistor Values for R Series Devices Digital Output Lines By default, the digital output lines of the R Series devices output a high value of 3.3 V. According to the manual, to create a TTL signal with a 5 V high on the digital output lines, I need to add an external pull-up resistor. What is the output impedance of R Series devices and what value URL: http://digital.ni.com/public.nsf/allkb/D58C269F7771770E86256F490082E6C8