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Digital Line on PXI-7833 has Low Impedance When Used as an Input I am using a digital line on a PXI-7833 card for both output and input. According to the documentation, the digital line should have high impedance when used as an input. Why do I see low impedance on mine? URL: http://digital.ni.com/public.nsf/allkb/06D1FC6B574024C986257253005D8E92

Compatibility of Digital I/O lines on the 78xx R series FPGA RIO Boards Are the digital lines on 78xx series RIO FPGA devices compatible with CMOS and/or TTL logic? URL: http://digital.ni.com/public.nsf/allkb/9B696F0E345E01A5862571870055634E

Compatibility Information of LabVIEW Real-Time with NI-RIO I am not able to use LabVIEW 7.1 and program FPGA’s using NI-RIO 2.X and higher through a real time controller. It requires an upgrade of LabVIEW. What is the problem? URL: http://digital.ni.com/public.nsf/allkb/47C7186E9F7716E98625714F007B571F

Error 1073807346: Error Occured at VISA Open and NI-RIO Open: Given Session or Object Reference is Invalid I am done writing and compiling my FPGA code and I want to run it. However, when I use the Open FPGA Reference and Invoke nodes on my host VI, when I hit the Run button, I get the following error:Error occured at VISA Open and NI-RIO open. The given session or object reference is URL: http://digital.ni.com/public.nsf/allkb/8203C68AF60F4259862571490077FFF3

Unable to Open Session to “visa://IP Address/PXI2::15::INSTR” I have installed the necessary software and configured all hardware for my PXI controller, but each time I try to access any of the devices I get the following error:Unable to open session to “visa://192.168.99.5/PXI2::15::INSTR” URL: http://digital.ni.com/public.nsf/allkb/293080923B466C9A86257141005775FD

Erasing FPGA Flash Memory Problem: How can I erase the contents of the flash memory on my FPGA board? Solution: If you have the NI-RIO Driver 2.1 (or later) installed on your computer, then this can be done by using the RIO Device Setup Utility. This utility can be invoked through an open LabVIEW project (8. URL: http://digital.ni.com/public.nsf/allkb/4789525480C3B78C8625714000746BFD

How Do I Synchronize the FPGA Clock in my R-Series Intelligent I/O Board to my PXI clock? I would like to synchronize the FPGA clock of my R-series PXI board to the 10 MHz clock in the PXI backplane. Where can I make this setting? URL: http://digital.ni.com/public.nsf/allkb/D108D4AF937524CA862570FF004C2A48

How Do I Synchronize the FPGA Clock in my R-Series Intelligent I/O Board to my PXI clock? I would like to synchronize the FPGA clock of my R-series PXI board to the 10 MHz clock in the PXI backplane. Where can I select this setting? URL: http://digital.ni.com/public.nsf/allkb/53306F0FDA486B298625738A007B130F

Analog Input Mode Configuration of 783xR FPGA Board In LabVIEW 8.0 and higher, the analog input mode of the FPGA board is software selectable from within the Project Explorer. Follow the steps below to configure the analog input configuration for your 783XR board if using LabVIEW 8.2. URL: http://digital.ni.com/public.nsf/allkb/08EF26D2E9041BC6862570E0001E442E

How to Reconnect to the LabVIEW FPGA Compile Server I disconnected my compiler client from the compile server and when I tried to reconnect to the FPGA VI by hitting Build in FPGA Project Manager it will recompile again. How can I reconnect to the server without compiling the VI again? URL: http://digital.ni.com/public.nsf/allkb/417E4AE5B5C74BEE862570BB00087933