Places FPGA in image path for on-board pre-pocessing and control applications Supports up to 10-tap, 80-bit acquisition at 20 MHz to 85 MHz pixel clock frequency 850 MB/s of available bandwidth over two Camera Link cables	Power over Camera Link (PoCL) support; can be used with PoCL cables to power cameras or without Optional digital I/O expansion card for extra triggering and isolation Requires LabVIEW FPGA Module software for image acquisition and processing

Overview

The NI PCIe-1473R is a cost-effective Camera Link frame grabber that works well for deployment systems and features a user-programmable FPGA for image processing. It supports 80-bit, 10-tap image acquisition from Camera Link 1.2 standard cameras up to 850MB/s over to Camera Link cables.

The PCI-Express form factor of the 1473R offers a cost-effective deployment alternative to complement the NI 1483 camera link adapter module and FlexRIO prototyping platform. This product is ideal for high-throughput systems in medical imaging, food sorting, semiconductor wafer alignment, flat panel display inspection, and more.

As the highest-bandwidth accepted imaging standard, Camera Link works well for high-resolution cameras and line-scan cameras. The NI PCIe-1433 also supports Power over Camera Link (PoCL) and can be used to power cameras through PoCL-enabled cables. You can access additional digital I/O lines using optional PCI and PCI Express I/O extension boards, which expose the following digital lines: eight bidirectional TTL, three optically isolated input, three optically isolated output, and one quadrature encoder.

NI LabVIEW and the LabVIEW FPGA Module are required to program the NI PCIe-1473R.

Requirements and Compatibility

OS Information Windows 7 Windows Vista Windows XP

Driver Information NI-IMAQ NI-RIO

Software Compatibility LabVIEW Development System LabVIEW FPGA Module

Application and Technology

The Benefits of LabVIEW FPGA

At the highest level, FPGAs are reprogrammable silicon chips. Using prebuilt logic blocks and programmable routing resources, you can configure these chips to implement custom hardware functionality without ever having to pick up a breadboard or soldering iron. You develop digital computing tasks in software and compile them down to a configuration file or bitstream that contains information on how the components should be wired together. In addition, FPGAs are completely reconfigurable and instantly take on a brand new “personality” when you recompile a different configuration of circuitry. In the past, FPGA technology was available only to engineers with a deep understanding of digital hardware design. The rise of high-level design tools, however, is changing the rules of FPGA programming, with new technologies that convert graphical block diagrams or even C code into digital hardware circuitry.

The LabVIEW FPGA Module can help you program an FPGA with a LabVIEW block diagram. Under the hood, the module uses code generation techniques to synthesize the graphical development environment to FPGA hardware. This block diagram approach to FPGA is well-suited for an intuitive depiction of the inherent parallelism that FPGAs provide. Use this module with commercial off-the-shelf (COTS) hardware to create FPGA-based measurement and control hardware whether or not you have worked with hardware description languages (HDLs).

Image Processing on the FPGA

FPGA image processing reduces the computational resources required for image analysis. Because the FPGA is a hardware resource, it frees the CPU to perform other operations. CPU intervention is not required to perform the analysis, so latency is significantly reduced from preprocessed input to processed output. In this case, the FPGA performs all of the image processing, which results in minimum system latency. You can send image information to the CPU for data storage or image display after processing is complete.

 

Figure 2. Image analysis is performed on the FPGA for minimal system latency.

You also can use an FPGA with a vision system’s processor to perform additional processing. Figure 3 shows how to preprocess with an FPGA while the CPU performs the more advanced processing algorithms. In this case, the FPGA performs bit-level processing such as filtering or edge detection. The preprocessed image is then sent to the CPU for image-level processing such as pattern recognition. System latency is still low in this case because the CPU has fewer functions to perform than it does in a traditional vision system. 

Figure 3. The image is preprocessed on the FPGA, which minimizes load on the CPU.

Many image processing algorithms are inherently parallel and hence suitable for FPGA implementations.  These algorithms which involve operations on pixels, lines, and region of interest do not need high-level image information, such as patterns or objects in the image.  You can perform these functions on small regions of bits as well as on multiple regions of an image simultaneously. You can pass the image data to the FPGA in parallel and, because a central processor is not required to process the data, process that data concurrently. Some examples of image processing functions that work well on an FPGA are listed below: 

Preprocessing  Image transforms Image operators Shading correction Bayer decoding Color space conversion 1D and 2D fast Fourier transform Filtering (smooth/sharpen) Binary morphology

Feature Extraction Edges, lines, and corners Binary objects Color Measurements Centroid Area measurements

In addition to the LabVIEW graphical design environment, LabVIEW FPGA supports a feature for HDL IP integration called Component-Level IP (CLIP). With CLIP, you can insert HDL IP into an FPGA target so VHDL code can communicate directly with an FPGA VI. CLIP also facilitates communication between the FPGA and external circuitry using existing HDL IP.