Using R Series Intelligent Data Acquisition for Bit-Error-Rate Test

Author(s):
Stephen Kulakowski - Harris RF Communications Division

Industry:
Aerospace/Avionics, Telecommunications, RF/Communications, Government/Defense

Products:
Data Acquisition, Digital I/O, LabVIEW, PXI/CompactPCI, FPGA Module

The Challenge:
Replacing traditional box instrumentation to support the testing of new and current product offerings.

The Solution:
Using National Instruments LabVIEW FPGA and R Series intelligent data acquisition to develop a more flexible system to test real-life file transfers while reducing cost per unit by 4X.

At Harris, an international communications and information technology company, we needed to replace our traditional box instrumentation in order to support testing of new and current product offerings. The main RF products we test are a data transmitter and a data receiver, with three different serial interfaces that must be validated. The older system supported a limited number of communication types, so we needed to find an off-the-shelf solution that was both flexible and scalable.

Using a National Instruments PXI-7833R FPGA module and an external wide area network (WAN) transceiver integrated circuit (IC) on a custom-printed circuit board, we implemented a complete serial bit error rate (BER) test system. The physical interfaces that needed to be validated were RS232, RS422, and RS485, the latter two being balanced interfaces for high-speed applications to 1.6 Mbps. The original system only supported 8-bit synchronous and asynchronous communication interface types, and at a much higher cost.

The interface to the R Series PXI-7833R module is a customized printed circuit board that utilizes a Sipex SP514 WAN interface IC for the different physical layer serial interfaces. The board also contains a temperature compensated crystal oscillator (TCXO) and a direct digital synthesis (DDS) circuit to generate the higher-speed clocks that the PXI-7833R uses to synchronize data. The 1 ppm TCXO is available to the user as a high-stability clock source for the UUT, and is available for future use for jitter testing and analysis. The data port interface is based on the EIA- 530 communication standard on a DB-25 connector. For added signal integrity at higher speeds, we ran coaxial lines for all the clock and data lines.

The target NI LabVIEW FPGA VI contains all the functionality of a typical BER test system. The VI accepts all user inputs to configure timing, physical interface, block size, handshaking signals, and preamble block size. We also had the option to insert one bit error for a system test. The bit error function randomly inverts a transmitted pattern bit and effectively modifies the transmitted data. These functions are also directly available from the host VI, which provides real pattern data and performs post-test analysis on the received data bytes to report BER,   bit errors, lost bits, and sync.

To repeatedly achieve synchronization within the system, the BER tester serially transmits preamble data of a user-specified size, generally less than 255 bytes. The FPGA code checks against and compares preamble bytes and stop bits to indicate to the user or test that synchronization has been validated. (This is also done at each specific byte compare within the pattern transmission.) If a failure occurs and there are significant bit errors, a file is generated for the user to compare sent and received data as seen by the BER tester.

If no sync is detected and preamble bits are still available, the target code employs a clock-shifting method to try to align received input data with preamble data values. If no synchronization occurs within the small preamble data block, the test system will report “no sync” on transmission and start a retest.

Essentially, the test usually involves two Harris products, one as a data transmitter and one as a data receiver, with an appropriate physical interface to the BER tester. The systems are usually connected through several feet of 50 ohm cable through an RF attenuator to assure good sensitivity and a high signal-to-noise ratio between the communication products.

A pre-specified random or pseudorandom data pattern is transferred to the transmitter system under test at a specified baud rate; the new BER tester can test at rates up to 1.6 Mbps. The information is modulated by the transmitter system and transmitted via RF at a specified carrier frequency. The receiver system receives the RF, demodulates it, and retransmits it back to the BER test system. At that point, the BER test system algorithm compares received data with transmitted data deterministically and reports the number of byte errors. The transmitted and received data is stored in target memory and later retrieved by the host VI application to report pattern bit errors and compute pattern BER. The BER test application algorithm also reports lost bits and synchronization time.

To achieve high-speed serial data processing to 1.6 Mbps, the application needed to compile and run at an FPGA clock speed of 80 MHz. We needed the data to be processed within 20 nS data resolution, and with the new system, we have now guaranteed target process time of 12.5 nS per bit. This is critical for relatively slow internal memory operations and real-time data comparison. We optimized the target VI to compile the application repeatedly at 80 MHz on multiple test systems.

We implemented deterministic data comparison using direct pattern memory comparison with the LabVIEW FPGA customizable memory block. The memory block was necessary to increase the payload data transfer and compare; otherwise, only very small data blocks would be transferable. Currently, up to a 30 Kbyte data pattern is available to the user in a drop-down menu.

Calling the target software from the host VI is a critical integration step to support full ATE product testing. Our current test software structure uses LabVIEW and NI TestStand. The test unit has the ability to execute a self-test using a loop-back cable that ties clock and data together, as well as using an SPDT switch to emulate modem handshaking lines required to validate the test setup. The test should always result in a zero loss result, meaning complete sync, 0 bits lost, and 0 bit errors.

One of the problems we encountered when trying to find an off-the-shelf solution that supports the PXI test platform was finding options that were customizable to work with our product communication interface and test. The first instrument option we found did not meet the interface requirements of our product base.

With the LabVIEW FPGA test option, we can test several serial communication physical layers without bulky interface cards. The new instrumentation also provides much added flexibility to test real-life file transfers and possibly serialized images between systems. It is also a PXI-based solution. The new system reduces cost per unit approximately 4X and offers customization capability to communication interfaces that have added test requirements.

We are currently investigating very high-speed systems (greater than 2 Mbps) using two PXI-7833 reconfigurable FPGA modules.

For more information, contact:

 

Steve Kulakowski

Test Engineer

Harris RF Communications Division

Rochester, NY 14610

 

 

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