FPGA-Based Real-Time Implementation for Direction of Arrival Estimation Algorithm Using QR Decomposition

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"We selected NI hardware from the PXI platform and FlexRIO and programmed it using LabVIEW software and the LabVIEW FPGA Module. Working with NI hardware and software made the implementation process easier and more efficient. "

- Dr. Nizar Tayem, Prince Mohammad University, Chair and Asst. Processor

The Challenge:
Our research team needed to implement a complex direction of arrival (DOA) estimation algorithm on hardware (FPGA) with high efficiency and throughput, and utilizing the least amount of hardware resources.

The Solution:
We used the NI PXI platform, FlexRIO hardware, and the LabVIEW FPGA Module to design and implement a complete DOA estimation hardware prototype that we can use to experimentally validate the performance of the system. The prototype receives source signals impinging on an antenna array, builds a received data matrix, and passes it on to the FPGA target that runs the DOA estimation algorithm to locate the source signals in real time.

Dr. Nizar Tayem - Prince Mohammad University, Chair and Asst. Processor
Abdulrahman Alhamed - King Saud University
Tariq Alshawi - King Saud University
Saleh Alshebeili - King Saud University
Ahmed Hussain - Prince Mohammad University

With rapid advances in the different fields of communication technologies, direction of arrival (DOA) estimation finds important practical applications in areas such as channel estimation and equalization, echo and interference cancellation, source localization in radar and sonar systems, beam forming smart adaptive antenna arrays in wireless mobile communications systems, and MIMO systems. The majority of research work reported in these areas has focused on numerical simulations of the algorithms for DOA estimation to establish accuracy and efficacy. However, due to the practical significance of these problems, we must implement and test these algorithms on real hardware to validate their viability in terms of computational speed, memory requirements, and implementation cost in hardware. In addition, most applications require DOA estimates be computed in real time (with computation speeds of the order of a few microseconds or even nanoseconds) such as in tracking a fast-moving target using a radar or sonar. So, the challenge is to implement DOA estimation algorithms in hardware efficiently, with high throughput and low latency, and build a complete hardware prototype (with signal transmitters and receivers with antenna array) for experimental validation of the DOA estimation algorithms.

Our research team comprises faculty members from the Department of Electrical Engineering at Prince Mohammad University (Al Khobar, Saudi Arabia) and research staff from Prince Sultan Advanced Technologies Research Institute (PSATRI) at King Saud University (Riyadh, Saudi Arabia). The team is involved in collaborative work in the development of efficient DOA estimation algorithms and their implementation in hardware for practical applications in both civilian and military areas.

We carried out the work reported in this case study using NI hardware and software. Prince Mohammad University houses an NI Center of Excellence and has excellent resources required for the research work.


Proposed DOA Estimation Algorithm

Algorithms for DOA estimation involve real-time processing, high speed and accuracy constraints, and complex number calculations. Such algorithms make hardware realization challenging for designers facing tasks in which choosing the most efficient algorithm has a vital role in the performance of the implementation. The technology advancement in integrated circuits (ICs), such as FPGA, made this implementation possible because a large quantity of logic gates was available in a single chip.

Several factors determine DOA algorithm performance, such as the size, number of elements, and spacing of the antenna array as well as different configurations of impinging signals. Many DOA techniques exist, which are based on analysis of the covariance matrix using eigenvalue decomposition (EVD) or analysis of the received data matrix using singular value decomposition (SVD). Both EVD- and SVD-based algorithms involve separating noise and signal subspaces that can be used to infer angles of arrival of impinging signals.

The work reported in this case study proposed a DOA estimation algorithm based on QR decomposition (QRD). QRD is well known for its stability and it has several advantages in estimating the DOA for multiple incident sources. First, QRD has much lower computational complexity compared to SVD, which has been widely used in DOA estimation. Second, QR factorization maintains accurate information about the data matrix rank and numerical null space. Third, it provides an efficient and robust solution for solving the least square problem often encountered in array signal processing and spectral estimation. These advantages make DOA estimation based on QRD beneficial in practical applications.


Hardware Architecture

We implemented the proposed architecture using Xilinx Virtex-5 SXT FPGA with 512 MB of onboard DDR2 DRAM. We partitioned the system design into seven main modules, each of which represents one of the main algorithm operations. We pipelined the complete architecture so data flows from one module to the next one, which permits high throughput implementation for the chosen algorithm. Figure 1 shows the data flows between the main modules and the major interior sub-modules.

Figure 1. Hardware Design of DOA Estimation Based on QRD


Hardware Prototype

Figure 2 illustrates the hardware prototype that we built to implement the proposed DOA algorithms for the real-time estimation of DOA angles. The prototype includes the following main modules:

  • The host PC module implements simulation models for realistic scenarios based on various RF source layouts and configurations to be used for data generation.
  • The target FPGA run-time engine implements the proposed methods using various FPGA processing elements (CLB1, LUT2, DSP3) while exploiting multi-clock rate processing with intra-module buffering to achieve a low-latency and high-bandwidth data processing pipeline. (1 - CLB: Configurable Logic Block, 2 - LUT: Lookup Table, 3 - DSP: Digital Signal Processor)

Figure 2. Different Modules and Blocks Developed and Assembled in This Project


We implemented the host PC module using a regular LabVIEW environment and the NI PXI platform; whereas, we implemented the target FPGA module using the LabVIEW FPGA Module on the target FlexRIO Xilinx FPGA. We designed the FPGA target prototype for efficiency in terms of resources utilization, accuracy, and speed.

The host PC collects data received from the RF receivers available in the NI PXI platform and passes it on to the target FPGA through a first-in-first-out (FIFO) queue using direct memory access. The target FPGA then reads the data from the FIFO and computes the DOA estimates in real time.

Finally, the host PC analyses parameters such as standard deviation and mean of the DOA estimates computed by the FPGA and generates performance metrics.


Verification and Testing

Figure 3 shows the system model for the hardware implementation and verification of the proposed DOA estimation algorithms. The RF transmitter unit consists of two signal generators that generate two uncorrelated signals at a frequency of 1 GHz. The RF receiver end consists of a ULA (uniform linear array) of four omnidirectional antennas, a PXIe-5601 RF downconverter, PXIe-5622 digitizers, and a PXIe-7965 FPGA Xilinx Virtex-5 module. Each of the four RF downconverter modules has an input for a local oscillator that connects to the same clock signal generated by a PXIe-5652 RF signal generator module to transform the signal from RF stage to intermediate frequency stage. We use the output signals from the four digitizers to estimate the DOA of incident sources using the proposed QR decomposition. We used LabVIEW FPGA and the PXIe-7965 FPGA Xilinx Virtex-5 to implement the DOA QR method.  

Figure 3. PXI Platform for RF Transmitter and Receiver Units


After completion of the prototype implementing the proposed algorithms on the target FPGA, we rigorously tested the prototype under different test scenarios for the experimental validation and verification of the proposed DOA estimation algorithms.

We validated the FPGA architecture using realistic data. An RF transmitter on the NI PXI module acted as a source, and we deployed an antenna array on the receiver side to collect data for the target FPGA to use for DOA estimation. We also tested the prototype for source localization in the presence of two sources (see Figure 4).

Figure 4. Experimental Setup for DOA Estimation of Two Sources


Figure 5 shows the experimental results for DOA estimation of two sources. We experimented in five different locations 20 times. Figure 5 shows the average results of DOA estimations with an average error of 1.2025 o. The estimated DOAs closely correspond to actual directions with a slight discrepancy due to reflections.

Figure 5. Experiment Results of Two Sources Located at Five Different Locations


We found the NI platform to be the most suitable for hardware implementation of our DOA estimation algorithms. We selected NI hardware from the PXI platform and FlexRIO and programmed it using LabVIEW software and the LabVIEW FPGA Module. Working with NI hardware and software made the implementation process easier and more efficient.

We used LabVIEW software to configure hardware modules certified by NI in a block diagram, which is suitable for fast prototyping designs. LabVIEW provides numerous libraries of optimized communication and signal processing function readily available for implementation. Additionally, LabVIEW offers excellent hardware integration functions that we can configure to create high-bandwidth, low-latency data channels between different modules. This empowers designers to focus on system architecture and performance optimization rather than focusing on smaller data exchange modules.

The implemented algorithm outperforms state-of-the-art algorithms in efficiency and effectiveness by utilizing partial QRD to separate noise and signal subspaces. The proposed hardware architecture computes the DOA estimation for each sample in 20 clock cycles at a maximum frequency of 56.61 MHz on a Virtex-5 FPGA chip with ±0.0488% accuracy for a four-element antenna array system. A bit-word length study shows that 16 bits is a suitable choice for the proposed architecture, which limits the error of the estimated angle to be less than 0.6 degrees. Extensive testing shows that the hardware implementation can reliably estimate DOA even at a low signal-to-noise ratio (SNR). For example, at an SNR of -2 dB the error is about 1.8 degrees. The hardware implementation is validated by comparing it to simulation results and through field tests using the NI PXI platform, LabVIEW, and the FPGA Xilinx Virtex-5. The proposed design compares favorably to other DOA implementation in the literature in terms of speed, performance, and efficiency.

We intend to continue our work in the development of more efficient DOA estimation algorithms, and implement and experimentally validate the developed algorithms using NI hardware and software.


Author Information:
Dr. Nizar Tayem
Prince Mohammad University, Chair and Asst. Processor
#1664, F041, COE Building, PMU
Al-Khobar,KSA 31952
Saudi Arabia
Tel: +966138498822

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