Parametric Test for Next-Generation Semiconductor Technologies

  Read in   |   Print Print

"With the in-fab ATE, we can now perform semiconductor process experiments that were previously impossible or came at a high wafer count cost. Performing these new experiments provides valuable insights that we, as an independent research organization, need in order to develop the next-generation process technologies for the semiconductor industry."

- Bart De Wachter, Researcher at imec, Semiconductor Technology and Systems Group

The Challenge:
Performing accurate electrical wafer-level tests in the semiconductor R&D fabrication (fab) process flow to detect process-related issues at an early stage, which would help us to rework the wafers at the right time to manage yield drops and to optimize the R&D process flow, reduce costs, and decrease the time to market of the newest chip manufacturing techniques.

The Solution:
Using the PXI platform with the new PXIe-4135 SMUs to build a measurement system for use inside the wafer fab, and programming this setup with LabVIEW, so we can keep all wafers inside, test them, process the results, and make much faster adjustments to the semiconductor process flow.

Bart De Wachter - Researcher at imec, Semiconductor Technology and Systems Group


Imec is a leading independent European research center for nanotechnology. We bring together key players from all layers of the semiconductor industry—from tool and material suppliers to integrated device manufactures and foundries to fabless and fab-lite companies all the way up to the application partners.

Thanks to our close partnerships with leading tool and materials suppliers, we can perform advanced semiconductor process development and offer our partners the industry’s most advanced research infrastructure housed within a state-of-the-art 300 millimeter wafer fab/clean room.

Our advanced semiconductor technology and processing R&D covers diverse topics including next-generation logic devices and advanced nano-interconnect research, all the way up to heterogeneous 3D stacked IC system integration, paving the way for future low-power mobile applications.

Figure 1. Inside the state-of-the-art 300 millimeter wafer fab


Challenges of the Fab Process Flow

We perform wafer/chip processing by sequentially running through hundreds of dedicated process steps called the process flow, starting from a blank silicon wafer and ending with an electrical functional chip. However, given the nature of the R&D environment and the complexity of the individual process steps, defects can occur over the length of the entire process flow and result in a significant yield drop of functional devices.

Electrical test of individual chips/devices on wafers, performed at an early stage in the process flow (embedded, so physically in fab) can allow early feedback of on-chip device performance (transistors, interconnects, circuits, and more) and allow early monitoring of the semiconductor processes. However, without an in-line electrical test setup, we did not have any feedback at critical points in the process flow. Because of this, we needed to take wafers out of the fab to test them on the existing parametric testers at a stage when the process was not fully completed. Wafers that went out of fab could not return for further processing due to contamination issues. Due to this, we experienced significant wafer losses and a big delay in the learning cycle and project deliverables.

Our R&D test chip vehicles consist of thousands of individual transistors, resistors, capacitors, and more with a wide variety of dimensions and architectures. Small demonstrator circuits may also be present. We need to test all of these devices to correctly characterize a specific semiconductor manufacturing process.

Taking all of this into account, we felt that an in-fab semiconductor automated test equipment (ATE) setup capable of handling 24/7 test operations could significantly speed up our R&D project deliverables and decrease the overall cost. We didn’t have a valid electrical test solution in our wafer fab, so we started looking for a versatile setup that could perform tests quickly and accurately to support our various industry affiliation programs. The setup needed to cover all our test needs for parametric and functional IC test, and we needed the ability to easily expand the setup for new tests on future semiconductor process technologies.

Figure 2. Abstraction of a Semiconductor Manufacturing Process Flow


Implementing an In-Fab, High-Throughput, and Highly Accurate ATE Setup 

In the past, we performed these tests on big parametric testers outside of our fab. They worked fine, but we had to produce double the amount of wafers because the tests were outside of the fab. We had to produce one set to keep in the fab and another set to test outside of the fab. This time consuming approach meant we had to take the lessons learned from the tested batch and apply them to the wafers currently still in the fab during the rest of the processing steps.

We wanted to reduce this overhead and look for alternative solutions. We wanted to select a supplier that would deliver good hardware and software service support. We noticed quickly that testers on the market either focus on parametric test or functional test, but not both. Also, they usually take a long time to program, come in a fixed package, and are expensive.

We use the NI PXI platform in our laboratories for general test, validation, and measurement activities, and enjoy an outstanding relationship with NI. We knew NI could deliver the hardware and software service support if needed. Once we realized NI was working on a next-generation, highly accurate source measure unit (SMU), we saw an opening to build a cost-efficient system and improve our in-fab measurement capabilities.

Having insight into NI’s roadmap led to us engaging with them as an early adopter of new technology. We used the PXIe-4135 and PXI platform to build an in-fab ATE system that can run 24/7 and drastically decreases our project timelines and helps us avoid waste in wafers.

We used a probe station equipped with an automatic wafer handling system that could run unattended. A custom probe card was developed and all wafer-probing components were hooked-up to a 19” rack that we equipped with the PXI system and a third-party, low-leakage switch matrix to preserve the specifications of our four PXIe-4135 devices. Additionally, we used a PXI-4072 DMM, four PXI-6551 digital modules, a PXI-5142 digitizer, and a PXI-6259 M Series module for trigger signal generation.

The triax cables of the PXIe-4135 were critical for us to preserve the low leakage levels throughout the entire setup. Figure 3 and Figure 4 show a block diagram and the signal routing diagram of our final setup. Figure 5 and Figure 6 shows the actual setup in our wafer fab.

Figure 3. Block Diagram of Imec’s In-Fab Full-Automatic Wafer Test Setup

Figure 4. Signal Routing Diagram of Imec’s In-Fab Full-Automatic Wafer Test Setup

Figure 5. The complete Setup, driven by a LabVIEW GUI & the PXI platform, in Action Inside the Fab

Figure 6. The PXIe-4135 SMUs at the Heart of All IV and CV Parametric Tests

Programming the Setup with LabVIEW and Getting Initial Results

We developed, implemented, and benchmarked a library of LabVIEW parametric test routines on the in-fab ATE using the PXI modular instruments for measurements on process monitor structures. We implemented customized LabVIEW test sequences for fully automated, unattended wafer test at several stages of the process flow. These sequences control and synchronize the NI instrumentation, the switch, the probe station, and the auto loader. Using LabVIEW, we logged all data in an imec data warehouse-compatible format to allow a smooth overlay of electrical data with other inline (optical) metrology data and giving way to in-depth process analysis.

A typical SMU-Transistor hookup scheme consists of applying the four PXIe-4135 SMUs to the gate, drain, bulk, and source terminals (Figure 7) and using individual force and sense connections through the switch matrix to rule out parasitic components. We submitted a complete LabVIEW transistor test suite on wafer including on-state/off-state current measurements, sweep measurements, threshold voltage extraction procedures, and more, and benchmarked all the results with high-end third-party instrumentation. Figure 8 shows that the PXIe-4135 SMUs are on par with the high-end third-party instrumentation, for IV- and even for CV measurements.

Figure 7. A typical SMU-Transistor hookup scheme using four PXIe-4135 SMUs

Figure 8. The benchmark results show that the PXIe-4135 SMUs are on par with high-end third-party instrumentation


PXIe-4135 and PXI Platform Impact on Our Fab Activities

With the in-fab ATE, we can now do experiments that were previously impossible or came at a high wafer count cost. Performing these new experiments provides valuable insights that we, as an independent research organization, need in order to develop the next-generation process technologies for the semiconductor industry. We can share with you the impressive improvements for one of these experiments:

Figure 9. Initial Results


The ATE setup that we built has become an indispensable tool for monitoring imec’s leading-edge semiconductor processes. All wafers coming over for electrical test can resume processing afterwards. There’s no need to take the wafers out of the fab anymore. This saves dozens of wafers a year for each of our industry affiliation programs. The learning cycle has become significantly shorter as well, which means we can finish projects sooner and perform more research in the same amount of time.

Whenever the embedded electrical test, followed by fast data analysis, proves that process conditions are out of spec and need to be tweaked, we can pull wafers back one or more steps in the process flow for a complete rework with updated process conditions. We can test again and continue processing or iterate the rework/test cycle time and time again. We have reduced the wafer loss caused by experimental/bad processing significantly.

One of our process integration engineers said, “In-line electrical test has become the only way to prove that we obtain valid process conditions. We cannot wait with test until the wafers have finalized processing as it would lead up to one month of delay in the learning cycle. In-line electrical measurements can capture many process related issues originating from patterning, metallization, and planarization steps, at an early stage in the wafer manufacturing process.”


Conclusion and Next Steps

The PXIe-4135 has proven to be a highly accurate SMU and can double as a Capacitance–Voltage (CV) measurement unit as well, saving costly expansion of instruments and test channels.

Demand for in-line testing has grown significantly over the last months and continues to do so. Increasing the test throughput and reducing the overall test time are among our challenges. Wafer fab cycle time is extremely important.

To tackle these challenges, we plan to improve and extend our LabVIEW parametric test procedure library and potentially evaluate TestStand software for a higher level of automation, operator friendly usage, and easy data handling.

Figure 10. Fab operator at work at the setup

Author Information:
Bart De Wachter
Researcher at imec, Semiconductor Technology and Systems Group
Kapeldreef 75
Leuven B-3001
Tel: +32 16 28 81 04

Bookmark and Share

Explore the NI Developer Community

Discover and collaborate on the latest example code and tutorials with a worldwide community of engineers and scientists.

‌Check‌ out‌ the‌ NI‌ Community

Who is National Instruments?

National Instruments provides a graphical system design platform for test, control, and embedded design applications that is transforming the way engineers and scientists design, prototype, and deploy systems.

‌Learn‌ more‌ about‌ NI