Probing of Large-Array, Fine-Pitch Microbumps for 3D ICs
"Engineers have long considered it impossible to probe these microbumps because the arrays are too large (≥1,000) and the pitches too small (≤40 µm). We developed a solution: a fully automated system to characterize prototype probe cards for large-array, fine-pitch microbumps on advanced test wafers using the Semiconductor Test System (STS) from NI."
- Ferenc Fodor,
Performing die tests prior to stacking 3D ICs to achieve sufficient compound stack yield by probing the interconnect microbumps for pre-bond test access.
Building a unique fully automatic system to characterize prototype probe cards for large-array, fine-pitch microbumps on our advanced test wafers using NI PXI instruments and the Semiconductor Test System (STS).
Ferenc Fodor - imec vzw
Bart De Wachter - imec vzw
Erik Jan Marinissen - imec vzw
Jörg Kiesewetter - Cascade Microtech, a FormFactor company
Ken Smith - Cascade Microtech, a FormFactor company
3D-Stacked ICs to Conquer the World
The research on 3D stacked IC (3D-SIC) technology has advanced to the point that virtually all semiconductor companies have now released or announced 3D-SIC products, or are developing such products in stealth mode. In 3D-SIC packages, multiple chip dies are stacked vertically, which results in a dense integration, possibly involving heterogeneous technologies, in an ultra-small footprint with considerable benefits for performance, power, and cost.
One challenge in stacking ICs is to retain a high compound yield and not include faulty dies. This requires testing the dies before stacking them, for example, through the interconnect microbumps. But engineers have long considered it impossible to probe these microbumps because the arrays are too large (≥1,000) and the pitches too small (≤40 µm). We developed a solution: a fully automated system to characterize prototype probe cards for large-array, fine-pitch microbumps on advanced test wafers using the Semiconductor Test System (STS) from NI.
Imec is the world-leading R&D center for nano-electronics and digital technology, headquartered near Leuven, Belgium, and with 3,500 researchers. We use state-of-the-art infrastructure, including our 200 mm and 300 mm wafer fabs, to perform research for a multitude of industries, including eight of the top 10 semiconductor companies. Our research program on 3D system integration is an imec Industrial Affiliation Program in which our own staff work alongside engineers from our industrial partners, key suppliers, and leading academic partners toward radical innovation and pre-competitive development.
Imec has contributed to the field of 3D-SICs for over a decade through research into:
• Through-silicon vias (TSVs) that allow making electrical connections to a silicon substrate’s back side
• Dense microbump interconnects between stacked dies
• Wafer thinning, bonding and debonding
• Various (die-to-die, die-to-wafer, and wafer-to-wafer) stacking approaches
We have also studied architecture, design, manufacturing, test, reliability, and thermal aspects of 3D-SICs through simulations and actual measurements on numerous test chips.
Figure 1. Cross Sections of 3D-SICs
Schematic (left), Photo Cross Section of Two Stacked Dies (right)
Challenges in Probing 3D-SIC Microbumps
Due to its many high-precision steps, semiconductor manufacturing is prone to defects. Therefore, every IC needs to undergo electrical tests to weed out defective parts and guarantee product quality. This is also true for 3D-SICs, which typically contain complex die designs in advanced technology nodes, and therefore need to be tested through today’s most advanced test and design-for-test approaches.
In addition, a number of test challenges are unique to the 3D-SIC stacking process itself. One of these is testing dies prior to stacking, which is essential to obtain acceptable compound stack yields and not lose good dies in a stack with one faulty die.
The non-bottom dies of the stacks have their functional access exclusively through large arrays of fine-pitch microbumps, which are too dense for conventional probe technology. A common approach to obtain pre-bond test access is to equip these dies with dedicated pre-bond probe pads . Unfortunately, this approach comes with drawbacks such as an increased silicon area and test application time, and a reduced interconnect performance. To avoid the many drawbacks associated with dedicated pre-bond probe pads, imec and key partners set out to enable probing directly on the microbumps, a task previously thought impossible.
State-of-the-art microbumps have the following specifications (see Figure 2):
• Landing bump: Cu, diameter 25 µm
• Top bump: Cu/Ni/Sn, diameter 15 µm
Figure 2. Typical State-of-the-Art Microbumps
Cu Bottom Microbump (left), Cu/Ni/Sn Top Microbump (center), Schematic Cross Section (right)
As an example probe target, we used JEDEC’s JESD-229 standard for Wide I/O single data rate DRAM (‘WIO1’) , which specifies the following array of microbumps (see Figure 3):
• Four banks of 50×6=300 bumps each, that is, 1,200 total microbumps
• Microbump pitch: 50 µm in horizontal direction; 40 µm in vertical direction
• Gap between banks: 6 columns in horizontal direction; 2 rows in vertical direction
Figure 3. JEDEC’s WIO1 Microbump Array 
The probe challenges for such a microbump array include the following.
1. Providing a test system with a sufficient number of channels for the large arrays of microbumps.
Test systems with 1,200 channels are usually expensive. A soft-docking cable interface with that many channels would be nearly impossible to connect and maintain.
2. Landing with all probe tips on the microbumps.
Advanced probe cards are non-see-through; hence, they require an advanced probe station that determines the probe-tip landing locations by means of a software overlay of images of the microbumps from a downward-looking camera and images of the probe tips from an upward-looking camera. We require sufficient positioning accuracy from both the probe tips with regard to each other, as well as from the probe station while stepping over the various dies on the wafer. As the smallest microbumps only have a radius of 7.5 µm, every micron counts! Even testing at room temperature requires a thermally stable probe chamber.
3. Establishing a proper electrical contact between probe tip and microbump.
The quality of the probe contact is expressed by the contact resistance Rc in Ohms. Rc depends on the metallurgy of the microbumps and the shape and material of the probe tips, but also on the amount of force with which the probe station presses the wafer against the probe tips (over-travel) and the cleanliness of the probe tips. Hence, while operating the probe station, we need to carefully consider the over-travel of the wafer chuck, and the recipe and interval of the automated tip-cleaning procedure, also because they have a major impact on the lifetime of the probe tips.
4. Probe marks, if any, should not negatively impact the stack’s interconnect yield.
The prime function of microbumps is to form a reliable electrical connection between two stacked dies. Marks, caused by the probe tip, should not deteriorate the interconnect stacking yield. Consequently, the probe marks should be limited in topology, or (for Sn bumps) be erasable through a reflow process.
5. The approach should be economically feasible.
Pre-bond test is constrained by cost: it should not cost more to perform the test than to skip it (and catch the same defects with another test later in the manufacturing flow). Probe cards are consumables and the price of the advanced probe cards required for microbump probing should not be prohibitive.
Demonstrating Feasibility of Microbump Probing With the Help of NI
To address these challenges, we teamed up with leading probe card supplier Cascade Microtech (Oregon, USA), who provided us with prototypes of their advanced Pyramid® Rocking Beam Interposer (RBI) probe cards (see Figure 4a). These probe cards contain an IC-design-specific probe core which includes a thin film with MEMS-type probe tips (see Figure 4b). Cascade’s high-density probe cores support >1,200 core I/Os, which is sufficient for WIO1. The RBI probe tips require less than 1 gf/tip to make proper electrical contact. The heel of the tip makes physical contact to the wafer (see Figure 4c), such that the probe mark is typically only 6 µm × 1 µm (see Figure 7).
Figure 4. Pyramid RBI Probe Card and Probe Core
Probe Card (left), Probe Core (center), Probe Tips (right)
To prove the feasibility of microbump probing with these probe cards, we built a unique full-automatic test system (see Figure 5) consisting of (1) a dual CM300 probe station from Cascade Microtech (Germany), (2) a hard-docking STS test head with PXI test instruments from NI, (3) a test head manipulator from Reid-Ashman (Utah, USA), and (4) test program and data analysis software based on LabVIEW and developed at imec.
Figure 5. Fully Automatic Test System to Evaluate Microbump Probing
The NI STS test head is a T2 model that contains two PXI racks with test instruments. Rack 1 holds instruments for parametric and functional tests. Rack 2 is dedicated to microbump probing. It contains a PXI-4072 digital multimeter (DMM) connected to an ultra-wide switch matrix (SMX1–9) consisting of nine concatenated PXIe-2535 modules of 136 output columns each. This allows us to connect each of the four channels of the DMM under software control to any of the 9×136=1,224 SMX output columns. Figure 6 shows that the system supports two-point and four-point (Kelvin) resistance measurements between any pair of probe tips (for daisy chains) as well as between a single probe tip and all other probe tips ganged (for characterization of that single probe tip when all probe tips are shorted through the probed wafer).
Figure 6. Rack 2 in the STS Test Head for Large-Array Microbump Probing
Rack 2 (left), Rack 2 Supports Two- and Four-Point Resistance Measurements (right)
Results and Conclusion
On 300 mm test wafers (which we designed and manufactured in-house and contain microbumps with various metallurgies, pitches, diameters, and sizes), we successfully demonstrated the following:
• All WIO1 probe tips do land on the corresponding microbumps (see Figure 7).
• The actual contact resistance between probe tip and microbump is Rc ~ 0.1 Ohm. However, the resistance of the trace through the thin film membrane on the probe core is often included in the measurement: Rc ~ 5 Ohm (see Figure 8).
• Probe marks on Cu are small, while probe marks on Sn are larger, but can be removed through reflow. We demonstrated experimentally that there were no stacking interconnect yield differences between all four cases of bottom/top microbumps probed/not-probed .
• Through cost modeling, we demonstrated that, for single-site testing, the Pyramid® Probe cards, although expensive, financially outperform pre-bond testing through dedicated probe pads .
We conclude that, contrary to common belief, microbump probing is technically and economically feasible.
Figure 7. Small Probe Marks in all Four Corners of the WIO1 Microbump Array
Figure 8. Test Results for a 300 mm Wafer With WIO1 Microbumps
Fail-Count Wafer Map (left), Probe Map With the Rc Results of an Individual WIO1 Touch-Down (right)
We observed the following benefits working with NI products.
• The NI STS hard-docking test head enables us to make >1,200 instrument-to-probe connections, which would not have been feasible with a manual cable interface.
• The PXIe-2535 switch matrix modules allow concatenation up to an ultra-wide switch matrix with unlimited lifetime of the FET switches. Its unlimited simultaneous cross-point connection provides us with the ability to perform probe checks.
• The test times are short: we can do ~100 two-point resistor measurements per second.
• The NI test instruments come at affordable prices.
• LabVIEW provides an easy-to-program interface to the system.
• Although it is a user-defined, home-grown system, we get support from the local NI branch in Belgium and, if necessary, input from NI’s R&D specialists in Austin, Texas.
We now use the test system routinely to check the quality of imec’s internal test chips. In addition, there is great interest among our customers and partners to use this system for microbump probing on actual 3D-SIC products, so we are actively sharing our insights with them. Currently, we are working on probing 40 µm-pitch microbump arrays at elevated temperatures and even probing 20 µm-pitch microbump arrays.
Part of this work was performed in the project SEA4KET, Semiconductor Equipment Assessment for Key-Enabling Technologies (http://www.sea4ket.eu), sub-project 3DIMS, 3D Integrated Measurement System, which receives funding from the European Union’s Seventh Programme for research, technological development, and demonstration under grant agreement No. IST-611332.
 Jung-Sik Kim et al., ‘A 1.2V 12.8GB/s 2Gb Mobile Wide-I/O DRAM with 4×128 I/Os Using TSV-Based Stacking’, IEEE International Solid State Circuits Conference (ISSCC’11), pp. 496–498, February 2011, doi:10.1109/ISSCC.2011.5746413
 Christian Freund. ‘Wide-IO DRAM – ST-Ericsson’s First Mobile Processor Using TSV 3D-IC Technology’, in CDNLive! EMEA, Munich, Germany, May 2011
 Jung-Sik Kim et al. ‘A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4×128 I/Os Using TSV Based Stacking’, IEEE Journal of Solid-State Circuits, 47(1):107–116, January 2012, doi:10.1109/JSSC.2011.2164731
 JEDEC Standard, ‘Wide-I/O Single Data Rate’, JESD229, December 2011
 Erik Jan Marinissen, Bart De Wachter, Ken Smith, Jörg Kiesewetter, Mottaqiallah Taouil, Said Hamdioui, ‘Direct Probing on Large-Array Fine-Pitch Micro-Bumps of a Wide-I/O Logic-Memory Interface‘, IEEE International Test Conference (ITC'14), Seattle, Washington, USA, October 2014, doi:10.1109/TEST.2014.7035314
 Mireille Matterne, Bart De Wachter, Ferenc Fodor, Erik Jan Marinissen, Jörg Kiesewetter, Mario Berg, Torsten Kern, Ken Smith, Eric Hill, ‘A Full-Automatic Test System for Direct Probing of JEDEC Wide-I/O Micro-Bumps’, IEEE European Test Symposium (ETS’16), Amsterdam, the Netherlands, May 2016
Bookmark and Share
Explore the NI Developer Community
Discover and collaborate on the latest example code and tutorials with a worldwide community of engineers and scientists.
Who is National Instruments?
National Instruments provides a graphical system design platform for test, control, and embedded design applications that is transforming the way engineers and scientists design, prototype, and deploy systems.