Developing a Digital Receiver System with Barker Code Matching Using NI PXI Express and LabVIEW


"We built our receiver system around NI FlexRIO modular FPGA hardware programmed with the NI LabVIEW FPGA Module, which helped us design the FPGA circuitry without needing to know VHDL coding. Through implementation of matching filter algorithms in FPGA, we achieved a significant increase in our processing performance."

- Suresh Repudi, Digilogic Systems Pvt Ltd

The Challenge:
Developing a digital receiver system to conduct measurements and evaluate the performance of RF system using off-the-shelf products.

The Solution:
Using NI PXI Express modular instruments and NI LabVIEW to create a digital receiver system for pulse compression techniques.

Suresh Repudi - Digilogic Systems Pvt Ltd
K Siddaiah - Digilogic Systems Pvt Ltd

Pulse compression is a signal processing technique often used to augment distance resolution as well as signal to noise ratio by modulating the transmitted pulse. Pulse compressions increase the transmitted average power while retaining the range resolution of a narrow pulse width. It has better discrimination of target echoes in clutter and is less susceptible to jamming.

Two basic types of pulse compression are linear FM and phase coding. Both encode the transmitted pulse with information that is compressed (decoded) in the receiver of the system. Pulse compression can compress pulses with durations of many microseconds down to a tenth of a microsecond. The ratio of transmitted pulse width to compressed pulse width is called the pulse-compression ratio.

Phase coding the transmitted pulse involves shifting the phase of the transmitter RF during the pulse width. A binary code is the normal method used to determine the phase shift. With a binary code, the binary bits can determine if the signal will shift to an in-phase condition or a 180-degree out-of-phase condition with respect to the reference. Pulse compression of the encoded waveform involves decoding the phase shifts and comparing this to the stored code. By making a bit-by-bit comparison of the received signal to the transmitted signal, we can determine target detection at the point when the bits match. This type of circuit is known as a matched filter.

System Setup

Through LabVIEW software, we simulated the transmitted signal. To support digital pulse compression, a suitable transmitted signal is generated with the help of a 13-bit Barker code. The Barker code is frequently used in signals with good auto-correlation function and equal time side lobes The Generator comprises of a 13 bit Barker code (user pattern), a NI PXIe-5673, RF Signal Generator (figure1), a Pulse Generator and related mixers for signal modulation and multiplication. The Receiver end comprises of RF Vector Signal Analyzer and NI FlexRIO PXIe-7965R FPGA modules.

In the RF signal analyzer, we can view the power spectrum and corresponding IQ constellation plot (see Figure 2). Through peer-to-peer streaming technology in the system, an NI PXIe-5622 digitizer in an NI PXIe-1075 chassis uses peer-to-peer data streaming to directly send IQ data to an NI PXIe-7965R NI FlexRIO FPGA module for digital signal processing (matched filtering and correlation techniques) so devices in a system can share information without burdening other system resources.

Peer-to Peer Streaming

Programming peer-to-peer data streaming is greatly simplified with the NI-P2P driver. In this application, we obtain the baseband signal from the RF signal analyzer and send it to the FlexRIO using peer-to-peer streaming for demodulation. Simple peer-to-peer reader and writer nodes provide a first-in-first-out (FIFO)-based interface for data exchange. These nodes are similar to direct memory access and local FPGA FIFOs. Before data exchange is possible, the host must connect the writer stream on NI PXIe 5663, RF Signal Analyzer to the reader stream on FPGA through the NI-RIO and NI-P2P APIs on the host (shown in Figure 3). Depending on the configuration, we need only one or two VIs to connect the peer-to-peer streams so that data exchange takes place.

We configured gardener PLL parameters in host and passed them on to the FPGA for the recovering symbols at the rate of 20 MHz. These symbols are passed for the recovery of the phase at the rate of 32 MHz clock, where phase is converted into bits. These bits are sent to the pack/unpack block for unpacking the demodulation bits. The demodulation bits are input to the matched filter to increase the signal-to-noise ratio.

We implemented a matched filter as a cross correlator, simulated by multiplying the received signal with the recorded signal on the storage medium at a higher playback speed. This helps us test the presence of target at variable arrival time delays. The product is passed through a low-pass filter to perform integration. The cross-correlation receiver checks for the presence of a target by matching the coded received signal with the stored sequence. Figure 3 shows the compressed signal of one interval with equal side lobes and 13 times magnified amplitude. Because the cross correlation receiver and matched filter are mathematically equivalent, the simulated circuit is considered a matched filter. The same circuit is realized on a LabVIEW FPGA.

Benefits of NI System

We built our system around the NI PXI Express platform to meet our high performance requirements. First, the PXI Express backplane architecture gave us point-to-point communication between different instruments using direct memory access eliminating the need to send data through the host processor or memory for inter-module communication. NI peer-to-peer streaming technology provided a high-level abstraction so we easily connected the digitizer and FPGA in the system without worrying about the low-level implementation. Instead, we focused on the FPGA algorithms (implementation of matched filter and Barker code) that determine the imaging performance of the system.

We built our receiver system around NI FlexRIO modular FPGA hardware programmed with the NI LabVIEW FPGA Module, which helped us design the FPGA circuitry without needing to know VHDL coding. Through implementation of matching filter algorithms in FPGA, we achieved a significant increase in our processing performance.


The objective of compressing a signal, generating and acquiring it with modulated signal, finding the 13 bit Barker code is achieved using the PXIe platform. This system being a first of its kind using the modular architecture of PXI, this has the capability to scale it up in future. The implemented technique has no sidelobes and eliminates the use of mismatched filter. Eliminating mismatch filter reduces the match filter hardware complexity that means less area, power consumption and cost. Also, elimination of mismatch filter improves the performance of compression process. The implemented technique can be used in radar, sonar and ultrasonic applications.

Author Information:
Suresh Repudi
Digilogic Systems Pvt Ltd
Plot No 1-8-303/48/30 1st Floor, P G Road
Secunderabad 500003

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