Author(s):
Rick Garza -
Averna Technologies, Inc.
Delivering Quality While Reducing Risk
Averna delivers value to clients by helping them mitigate risk and accelerate, improve, and standardize product development initiatives through automated product testing and data management solutions and services. Because we are an NI Platinum Alliance Partner, a customer contracted us to work with its hardware design and test engineering teams to deliver design validation and manufacturing test solutions for new product development.
Because multiple circuit card assemblies (CCAs) comprise the final product, much of the design and validation testing was already underway, and the system was nearing integrated function testing, calibration, and final verification testing. We worked with the test engineering and design teams to develop these manufacturing test solutions, but the nature of the daughterboard devices under test (DUTs) limits test-point or connector-edge access for CCA-level functional test or in-circuit test. More importantly, the CCAs undergo a very costly heat-sink and shielding process during assembly, and it would be time-consuming to remove and repair any module failures that might occur later in the manufacturing process. A CCA-level functional test with high coverage would greatly reduce risk while increasing overall product quality.
System Design Using NI FlexRIO and LabVIEW FPGA
To develop a CCA functional test, we needed to determine how to communicate with the DUT. The customer hardware team had designed a custom interface board for fanning out DUT signals for test purposes (including interboard digital connectors), and mapped those to a very-high-density cable interconnect (VHDCI) connector that was pin-compatible with NI high-speed digital I/O (HSDIO) products. It would be difficult to code all of the bidirectional control logic from scratch using a standard HSDIO board and LabVIEW, and possibly too slow to interface with the DUT at the hardware level. As a result, we decided to develop a LabVIEW FPGA image on an NI FlexRIO module that could emulate host CPLD control logic in real time while communicating with the DUT.
The emulation development system consists of one NI FlexRIO and HSDIO module for emulation; one NI FlexRIO and HSDIO module for testing the emulation signals; DC power for the DUT; and measurement hardware to verify that the DUT communicates properly. The manufacturing test station only uses the emulation NI FlexRIO device, in addition to measurement hardware, for a fully functional test.
From a software perspective, the field-programmable gate array (FPGA) code consists of a host interface; an HSDIO hardware interface; a secondary HSDIO debug host and interface; and the core FPGA emulation code, as shown in Figure 1. We used the second NI FlexRIO module to capture signals generated by the main emulation NI FlexRIO module through the DUT, but once we proved clocking, signal levels, proper handshaking, and valid address data, we no longer needed the second module. From that stage, the emulation NI FlexRIO module connects directly to DUT daughterboards for functional verification using the emulated control signals.
Figure 1. Software Overview
Using VHDL IP for Emulation Control Code
Working with the digital hardware designer, the customer successfully converted the CPLD VHDL code into a leaner version more suitable for manufacturing test. Using the core features of the LabVIEW FPGA Module, we integrated that IP using the Component-Level IP (CLIP) Node, thus embedding much of the control logic in an NI FlexRIO FPGA module, as shown in Figure 2. NI support and documentation greatly helped us translate the VHDL code into a working CLIP Node we could use for FPGA development. We went through several iterations based on feedback given to the digital designer from our debug test data. We corrected issues such as clock noise and jitter levels using an oscilloscope and the debug NI FlexRIO and HSDIO module. Once we established signal integrity, we found communication errors very quickly using both of the NI FlexRIO devices for interactive testing. For example, the CLIP code runs in a different clock domain than the FPGA code for its internal needs. Some signaling required single-cycle timing, whereas others, such as reset lines, required additional clock cycles. To accomplish the additional clock cycles and latch states for control lines, we used feedback nodes and control logic, as shown in Figure 2.
Figure 2. Example CLIP Node
Test Automation Success Using Advanced Emulation Control
Once the digital timing was working correctly and the CLIP interface edits were finalized, we had a highly stable and repeatable DUT communication and control interface. The hardware synchronization and deterministic nature of an FPGA provided a control stimulus to the DUT as if it were connected directly to its target system. From a test development perspective, we could reuse almost all of the top-level functional tests defined for the modular system for the CCA functional tests by simply replacing the CPLD communication calls with the emulation FPGA host interface. This was a huge benefit to both the hardware design team and the test engineering team for reducing code development efforts and ensuring tight correlation across test data.
Conclusion
Using the power of LabVIEW FPGA and its built-in IP integration, we greatly reduced the complexity and shortened the development cycle of a stable manufacturing test platform for a highly complex product. Testing at the functional CCA level with maximum test coverage reduces risk during each phase of the manufacturing process. This translates into reduced manufacturing costs, shorter production cycle times, and a higher-quality product. Another benefit is the ability to reuse the emulation design concept in future products. Developing the emulation code earlier during design could even further reduce time to market by providing functional and digital control testing during prototype phases.
Author Information:
Rick Garza
Averna Technologies, Inc.
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